16.1 Processor Modes

Processor Operating Modes


The three operating modes are listed in order of decreasing system privilege:

Selection between the three modes can be made by the operating system (when in Kernal mode) by writing into Status register's KSU field. The processor is forced into Kernel mode when the processor is handling an error (the ERL bit is set) or an exception (the EXL bit is set). Table 16-1 shows the selection of operating modes with respect to the KSU, EXL and ERL bits.

Table 16-1 also shows how different instruction sets and addressing modes are enabled by the Status register's XX, UX, SX and KX bits. A dash ( "-" ) in this table indicates a "don't care." For detailed information on the address spaces available in each mode, refer to section titled, "Virtual Address Space," in this chapter.

The R10000 processor was designed for use with the MIPS IV ISA; however, for compatibility with earlier machines, the useable ISAs can be limited to either MIPS III or MIPSI/II.

Table 16-1 Processor Modes




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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